| Telecom Vacancies Description |
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Employer: Analog Solutions
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| Address: |
204 Lakeside Plaza Suite 140 |
| City: |
London |
| State / Province: |
TN |
| Country: |
USA |
| Zip code: |
37774 |
| Phone number: |
+1 865-458-4421 |
| Fax number: |
+1 865-458-4424 |
| E-mail: |
Send Message
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| Company URL: |
www.analogsolutions.com/ |
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Employer need: Power Supply Designer
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Telecom Vacancy Description:
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| Job Category: |
Engineering |
| Timing: |
Full Time |
| Place of work/City: |
San Jose |
| Place of work/Country: |
USA |
| Application Documents: |
CV/Resume |
| Job description, requirements : |
EXPERIENCE and REQUIREMENTS
• BS Electrical Engineering (MS preferred)
• 5+ years experience designing power supplies
• 20% travel to Central Valley, Northern Nevada, and Utah
• Bay area candidates preferred |
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Employer need: RF Applications Engineer
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Telecom Vacancy Description:
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| Job Category: |
Engineering |
| Timing: |
Full Time |
| Place of work/City: |
Fremont |
| Place of work/Country: |
USA |
| Application Documents: |
CV/Resume |
| Job description, requirements : |
EDUCATION and EXPERIENCE
• BS Electrical Engineering (MS preferred)
• 5+ years experience with all radio architectures (Dual Conversion, High IF, Low IF, Direct Conversion)
• Must understand basic circuit techniques (Mixers, LNA, Filters)
• Must have familiarity with Data Converters, how they work, how they are evaluated, what metrics are important to a designer (Pipeline Converter experience preferred)
• Must have good Mixed-Signal circuit board design experience (Converters, Buffer Amps, Filters…) |
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Employer need: Senior IC Layout Mask Designer
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Telecom Vacancy Description:
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| Job Category: |
Engineering |
| Timing: |
Full Time |
| Place of work/City: |
Atlanta |
| Place of work/Country: |
USA |
| Application Documents: |
CV/Resume |
| Job description, requirements : |
| Candidate should have experience in assisting design teams in the floor planning and control channel routing of highly complex mixed signal integrated circuits. Must have demonstrated experience in performing all top level layout verification tasks necessary to tape out to external foundries; experience with assembly of multiple chips into the complete reticle is a plus. Experience with Cadence Virtuoso™ and Virtuoso-XL™ front end layout, along with Mentor Calibre™ verification and parasitic extraction tools, is required; experience with Cadence Assura™ verification and parasitic extraction or RF extraction tools such as ColumbusRF™ is a plus. Requires having worked with BiCMOS technologies at 0.5 um and/or below; experience with CMOS technologies at 0.25um and 0.18um is also required, 0.13um and below is a plus. Experience with customization of foundry PDK components is also a plus. Ability to perform first line support of the layout and verification tools is a big plus. |
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Employer need: Sr. Analog IC Designer
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Telecom Vacancy Description:
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| Job Category: |
Engineering |
| Timing: |
Full Time |
| Place of work/City: |
Santa Clara |
| Place of work/Country: |
USA |
| Application Documents: |
CV/Resume |
| Job description, requirements : |
Description
* This person will be the technical lead on integrated CMOS imager sensor products. These sensors have integrated ADC`s, DAC`s, power supplies, PGA`s, readout circuits and digital controllers. They will oversee the specification, design, simulations, noise analysis, layout, and bring up of image sensors as well as designing some of the analog blocks on the chip. They will also be responsible for innovating in order to add new features, improve the product, reduce die size and increase yield. This position will be a mentor for the rest of the design team. |
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